1. Field of the Invention
The present invention relates to a programmable logic device. Further, the present invention relates to a semiconductor device using the programmable logic device, and an electronic device using the semiconductor device.
In this specification and the like, a semiconductor device means all types of devices that can function by utilizing semiconductor characteristics, and a transistor, a semiconductor circuit, and the like are each one form of the semiconductor device.
2. Description of the Related Art
Recently, a programmable logic device (PLD) such as a field programmable gate array (FPGA) or a complex programmable logic device (CPLD), in which the logic can be defined and changed by a user after manufacturing, has attracted attention to replace an application specific integrated circuit (ASIC) which is an integrated circuit for a specific use. The PLD has advantages such as reduction in development period and a high degree of flexibility for the change of the design as compared to the ASIC and, for this reason, has started to be incorporated in a variety of electronic devices.
For example, the PLD consists of a plurality of logic blocks and wirings connecting the logic blocks. By changing the function of at least one of the logic blocks, the function of the PLD can be changed. The logic block is formed using, for example, a lookup table (LUT) or the like. The LUT has a function of outputting a value corresponding to a pattern of an input value based on the pre-calculated table of the outputs for patterns of a plurality of input values (see Patent Document 1).
The LUT consists of a memory and multiplexers and can change the circuit structure with data stored in the memory. The data stored in this memory of the LUT or a memory that controls connections of the wirings is called configuration data, and the memory where the configuration data is stored is called a configuration memory. By rewriting the configuration data stored in the configuration memory, the circuit structure can be changed to a desired structure. Note that the configuration memory is a generic term for memory that exists in the LUT or a wiring connection circuit as described above and, in some cases, does not exist in one specific place.
For example, a 3-input 1-output LUT illustrated in FIG. 8A previously stores patterns of input values of three terminals I1, I2, and I3 (eight patterns in total) and output values corresponding to the input patterns and outputs the stored value in accordance with the pattern of the input values. In the case of a 3-input 1-output circuit formed of an AND circuit and an OR circuit illustrated in FIG. 8B, eight patterns of the input values of the input terminals I1, I2, and I3 and their output values (truth table) are shown in FIG. 8C. The 3-input LUT illustrated in FIG. 8A can form a desired logic circuit by using a 8-bit memory MEM and multiplexers MUX1 to MUX7 which form a binary tree circuit as illustrated in FIG. 8D.
In the case where the logic circuit illustrated in FIG. 8B is a hardware circuit, it is difficult to freely change the circuit structure after manufacturing; in contrast, in the case where a LUT is used to form the logic circuit illustrated in FIG. 8B, changing the value of an output terminal F can produce the same effect as changing the circuit structure. For example, in FIG. 8C, when the values of the output terminal F except the leftmost value are all 0, the logic circuit serves as a 3-input AND circuit; whereas when the values of the output terminal F except the leftmost value are all 1, the logic circuit serves as a 3-input OR circuit.